1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure for testing the semiconductor device.
2. Description of the Background Art
For ensuring the reliability of products, various tests are performed on semiconductor devices. The tests of semiconductor device include a test at a wafer level and a test on a packaged device prior to shipment. For operations in various kinds of test modes, the semiconductor device is provided with circuit elements corresponding to the respective test modes. These circuit elements are selectively set to appropriate states in accordance with a designated test mode so that short-circuiting between internal nodes, change of an operation mode and others are performed. The test at the wafer level specifically includes a test for determining whether an internally produced reference voltage is set at a predetermined voltage level or not, and a performance evaluating test for determining whether internal circuits of the semiconductor device satisfy predetermined operation characteristics or not. Final tests after packaging specifically includes a screening test (voltage stress accelerated test) for revealing a latent defect.
The types of tests made on the semiconductor device increase with increase in integration density and number of functions of the semiconductor device. Increase in number of the types of test modes results in increase in number of corresponding circuit elements and therefore increase in area of the chip occupied by the circuit elements dedicated to the test operations so that the chip area increases, and the cost increases.
Various test modes are designated by combinations of states of a plurality of signals (e.g., WCBR+super VIH+address key). In this case, a designated test mode must be accurately determined, and the device must be set to the state corresponding to the designated test mode. If the device is set to an erroneous test mode state, an intended test could not be performed and the performance evaluation of the semiconductor device could not be made accurately.
Voltage acceleration is performed for accelerated tests such as a life test or a screening test of the product. In the case of the voltage acceleration, the voltage acceleration must be performed efficiently for reducing a test time. For example, if an internal power supply voltage is changed in accordance with an external power supply voltage in a semiconductor memory device, an internal voltage higher than the internal power supply voltage also rises. Therefore, the internal power supply voltage can be raised only to a restricted level because break down voltage must be ensured in portions receiving the internal voltage. This results in a problem that voltage acceleration on all the internal nodes cannot be performed efficiently.
Further, screening must be effected on various portions by voltage acceleration for ensuring the reliability.